Long distance data transmission is usually in form of serial data transfer. Several specifications or for such long distance data transmission have been promulgated. Two of the most used specifications are the T1 protocol, widely used in the United States, and the CEPT protocol, commonly used in Europe.
In the T1 protocol the serial data is organized into 24 channels of 8 bits each (192 bits) preceded by a framing bit for a total of 193 bits. This 193 bit data packet constitutes a single frame of data. The CEPT protocol has 32 channels of 8 bits each for a total of 256 bits. This 256 bits also constitutes a single frame. The T1 bit rate is 1.544 megabits per second or 125 milliseconds per frame. The CEPT bit rate is 2.048 megabits per second or 125 milliseconds per frame. Thus, each frame of the CEPT protocol contains more bits and transfers these bits at a higher bit rate than the T1 protocol, but the time required to transfer a single frame of data in the CEPT protocol is equal to the time required to transfer a single frame of data in the T1 protocol.
A problem which arises in long distance serial data transmission is the asynchronization of the transmission and receiving clocks at data multiplexer locations. Neither the T1 protocol nor the CEPT protocol use a single clock which is synchronized throughout the data network, but rather rely on tightly specifying the data transmission rate to a tolerance of several hundred parts per million. However, since the transmission and receiving clocks at a multiplexer point are not synchronized, a method to compensate for this lack of synchronization is to provide a first-in, first-out (FIFO) buffer in which data is written into the buffer using the transmission clock frequency and read from the buffer at the receiving clock frequency. The FIFO thus acts as a buffer to absorb short term variations in frequency between the transmitting clock and the receiving clock.
However, the FIFO buffer by itself is not sufficient to compensate for long term frequency differentials because the excess data being written into or read from the FIFO would sooner or later be greater than the depth of the FIFO. In these conditions, the differences in the clocks are resolved by a "slip" operation in which a frame of data is either dropped completely if the transmission clock is faster than the receiving clock, or a frame of data is read twice in succession if the receiving clock is faster than the transmission clock. Both the T1 and the CEPT specifications require that the slip operation occur at frame boundaries. That is, a whole frame must be slipped the packet of data constituting a frame cannot be divided. In the T1 protocol the rising edge of the framing bit is coincident with the rising edge of the frame sync pulse and forms the boundary between frames. In the CEPT protocol the rising edge of bit 1 of the first channel forms the boundary between frames. However, in the CEPT protocol the position of the frame sync pulse may be coincident with the first bit of the first channel or may be coincident with the eighth bit of the 32nd channel depending on the convention being used.
A FIFO is a memory storage device in which data is sequentially written into the FIFO and sequentially read out from the FIFO. The reading and writing operations are independent of each other and thus the memory location being written into may be the same or different from the memory location being read from. Since the memory locations being written into or read from are advanced sequentially with the write clock and the read clock respectively, the FIFO does not have any external address lines.
It is convenient when discussing the operation of a FIFO to talk of a write pointer and a read pointer. The position of the write pointer is the location of the memory cell being written into, and the position of the read pointer is the location of the memory cell being read from at any point. In the ideal operation of a FIFO, data is written into the FIFO and read from the FIFO at the same rate so that each memory location is alternately written into and read from. However, if the write clock is faster than the read clock, then the write pointer will be sequencing through the address positions faster than the read pointer. At some point then, the write pointer will pass the read pointer and the FIFO will write data into memory locations before the previous data has been read out. Conversely, if the read clock is faster than the write clock, at some point data will be read from the same memory location twice before new data is written into the memory location. When the write pointer catches up with the read pointer or when the read pointer catches up with the write pointer, a collision or contention occurs. In order to avoid a collision, a FIFO generally has circuitry to warn of an impending collision.
Presently available from several suppliers are standard FIFOs. In order to warn of an impending collision, the standard FIFOs have an empty flag and a full flag which signal when the write and read pointers are within one byte of each other. In the standard FIFOs these "bytes" are 9 bits wide, having an extra bit for parity.
The standard FIFOs are not well suited for use with the T1 and CEPT protocols for several reasons. First, only 8 of the 9 bits can be mapped directly to a channel, thus either wasting memory space or requiring additional overhead logic. Secondly, the frame boundaries must be stored and correlated with external logic. Thirdly, one byte warning distance may be an insufficient warning in order to initiate a slip operation before a collision occurs.
Thus, it can be appreciated that it would be highly desirable to have a FIFO which would be able to slip on frame boundaries, which would provide sufficient warning of a collision to allow time for a slip operation before the collision, which would delete/repeat exactly one frame of data during a slip, and which is suitable for use with T1, CEPT, and combinations of T1/CEPT protocols.